1. Field of the Invention
The present invention relates to a liquid crystal display, and more particularly to a liquid crystal display that is adaptive for changing a supply sequence of a scanning pulse with which a plurality of gate lines are supplied to realize a one dot inversion, and a driving method thereof.
2. Description of the Related Art
Generally, a liquid crystal display controls light transmittance of liquid crystal cells in accordance with video signals to display a picture. An active matrix type of liquid crystal display having a switching device provided for each liquid crystal cell is advantageous for an implementation of moving picture because it permits an active control of the switching device. The switching device used for the active matrix liquid crystal display mainly employs a thin film transistor (hereinafter, referred to as “TFT”) as shown in FIG. 1.
Referring to FIG. 1, the liquid crystal display of the active matrix type converts digital input data into an analog data voltage on the basis of a gamma reference voltage to supply it to a data line DL and, at the same time supply a scanning pulse to a gate line GL, thereby charging a liquid crystal cell Clc.
A gate electrode of the TFT is connected to the gate line GL, a source electrode thereof is connected to the data line DL, and a drain electrode of the TFT is connected to a pixel electrode of the liquid crystal cell Clc and one end electrode of a storage capacitor Cst.
A common electrode of the liquid crystal cell Clc is supplied with a common voltage Vcom.
When the TFT is turned-on, the storage capacitor Cst charges a data voltage applied from the data line DL to constantly maintain a voltage of the liquid crystal cell Clc.
If a scanning pulse is applied to the gate line GL, the TFT is turned-on to define a channel between the source electrode and the drain electrode, thereby supplying a voltage on the data line DL to the pixel electrode of the liquid crystal cell Clc. In this case, liquid crystal molecules of the liquid crystal cell Clc are arranged by an electric field between the pixel electrode and the common electrode to modulate an incident light.
A configuration of the related art liquid crystal display including pixels which have such a structure is the same as shown in FIG. 2.
FIG. 2 is a diagram showing a configuration of a liquid crystal display of the related art.
Referring to FIG. 2, a liquid crystal display 100 of the related art includes a liquid crystal display panel 110 provided with a thin film transistor TFT that drives the liquid crystal cell Clc at an intersection where a plurality of data lines DL1 to DLm and a plurality of gate lines GL1 to GLn are crossed each other, a data driver 120 that supplies data to the data lines DL1 to DLm of the liquid crystal display panel 110, a gamma reference voltage generator 130 that generates a gamma reference voltage to supply it to the data driver 120, a backlight assembly 140 that irradiates a light onto the liquid crystal display panel 110, an inverter 150 that applies an AC voltage and a current to the backlight assembly 140, a common voltage generator 160 that generates a common voltage Vcom to supply it to the common electrode of the liquid crystal cell Clc of the liquid crystal display panel 110, a gate driving voltage generator 170 that generates a gate high voltage VGH and a gate low voltage VGL to supply them to the gate driver 130, a timing controller 180 that controls the data driver 120 and the gate driver 130, and a gate driver 190 that supplies a scanning pulse to the gate lines GL1 to GLn of the liquid crystal display panel 110.
The liquid crystal display panel 110 has a liquid crystal injected between two glass substrates. On the lower glass substrate of the liquid crystal display panel 110, the data lines DL1 to DLm and the gate lines GL1 to GLn perpendicularly cross each other. Each intersection between the data lines DL1 to DLm and the gate lines GL1 to GLn is provided with the TFT The TFT supplies data on the data lines DL1 to DLm to the liquid crystal cell Clc in response to the scanning pulse. The gate electrode of the TFT is connected to the gate lines GL1 to GLn while the source electrode thereof is connected to the data line DL1 to DLm. Further, the drain electrode of the TFT is connected to the pixel electrode of the liquid crystal cell Clc and to the storage capacitor Cst.
The TFT is turned-on in response to the scanning pulse applied, via the gate line which is connected to a gate terminal of the TFT among the gate lines GL1 to GLn, to the gate terminal thereof. Upon turning-on of the TFT, video data on a data line which is connected to a drain terminal of the TFT among the data lines DL1 to DLm are supplied to the pixel electrode of the liquid crystal cell Clc.
The data driver 120 supplies data to the data lines DL1 to DLm in response to a data driving control signal DDC supplied from the timing controller 180. Further, the data driver 120 samples and latches digital video data RGB fed from the timing controller 180, and then converts them into an analog data voltage capable of expressing a gray scale level at the liquid crystal cell Clc of the liquid crystal display panel 110 on the basis of a gamma reference voltage supplied from the gamma reference voltage generator 130, thereby supplying it the data lines DL1 to DLm.
The gamma reference voltage generator 130 receives a high-level power voltage VDD to generate a positive gamma reference voltage and a negative gamma reference voltage and output them to the data driver 120.
The backlight assembly 140 is provided at the rear side of the liquid crystal display panel 110, and is radiated by an alternating current voltage and a current supplied from the inverter 150 to irradiate a light onto the liquid crystal display panel 110.
The inverter 150 converts a square wave signal generated at the interior thereof into a triangular wave signal, and then compares the triangular wave signal with a direct current power voltage VCC supplied from the system to generate a burst dimming signal proportional to the result. If the burst dimming signal determined in accordance with the rectangular wave signal of the interior of the inverter 150 is generated, then a driving integrated circuit IC (not shown) controlling a generation of the AC voltage and a current within the inverter 150 controls a generation of AC voltage and current supplied to the backlight assembly 140 in accordance with the burst dimming signal.
The common voltage generator 160 receives a high-level power voltage VDD to generate a common voltage Vcom, and supplies it to the common electrode of the liquid crystal cells Clc of the liquid crystal display panel 110.
The gate driving voltage generator 170 is supplied with a high-level power voltage VDD to generate the gate high voltage VGH and the gate low voltage VGL, and supplies them to the gate driver 190. Herein, the gate driving voltage generator 170 generates a gate high voltage VGH more than a threshold voltage of the TFT provided at each pixel of the liquid crystal display panel 110 and a gate low voltage VGL less then the threshold voltage of the TFT. The gate high voltage VGH and the gate low voltage VGL generated in this manner are used for determining a high level voltage and a low level voltage of the scanning pulse generated by the gate driver 190, respectively.
The timing controller 180 supplies digital video data RGB which are supplied from a scaler (not shown) for processing an image to the data driver 120. Herein, the scaler (not shown) for processing an image is included in a system such as a TV set or a computer monitor, etc. Furthermore, the timing controller 190 generates a data driving control signal DCC and a gate driving control signal GDC using horizontal/vertical synchronizing signals H and V in response to a clock signal CLK to supply them to the data driver 120 and the gate driver 190, respectively. Herein, the data driving control signal DDC includes a source shift clock SSC, a source start pulse SSP, a polarity control signal POL, and a source output enable signal SOE, etc. The gate driving control signal GDC includes a gate shift clock GSC, a gate start pulse GSP, and a gate output enable signal GOE, etc.
The gate driver 190 sequentially generates a scanning pulse, that is, a gate pulse in response to the gate driving control signal GDC which is supplied from the timing controller 180 to supply it to the gate lines GL1 to GLn. In this case, the gate driver 190 determines a high level voltage and a low level voltage of the scanning pulse in accordance with the gate high voltage VGH and the gate low voltage VGL, respectively. Herein, the gate high voltage VGH and the gate low voltage VGL are supplied from the gate driving voltage generator 170.
When the related art liquid crystal display having such configurations is driven by a one dot inversion method as shown in FIG. 3, if the gate driver 190 sequentially supplies the scanning pulse to the plurality of gate lines GL1 to GLn as shown in FIG. 4, a polarity of an analog data voltage, which is supplied from the data driver, is alternately converted on the basis of the common voltage Vcom. Herein, the analog data voltage is supplied with the data driver 120. If a polarity of the data voltage is converted whenever the data line is supplied with a data voltage, a temperature within the data driver 120 is risen. As a result, the related art liquid crystal display has a disadvantage in that an internal circuit of the data driver 120 is degraded.